1. Field of the Invention
The present invention relates to a method and apparatus for emulating instructions of a legacy microprocessor and, more particularly, to an emulation system for a legacy microprocessor, such as a 32-bit microprocessor, which executes a compiled higher-order language, such as C/C++, in which the compiled code is structured such that data and instruction segments are structured, for example, as in Reduced Instruction Set Computer (RISC) microprocessors, wherein the legacy instructions are directly mapped to an equivalent instruction of the host processor, where possible, to improve the real-time performance of the system.
2. Description of the Prior Art
It is known that microprocessors are configured with different instruction-set architectures (ISA). The ISA determines the instruction set for a particular microprocessor. Application programs are executed by a microprocessor, normally written in a relatively high-level language, which, in turn, are compiled into machine instructions compatible with the instruction set for a specific microprocessor.
Due to the age obsolescence of many existing microprocessors and corresponding slow speed, it is often desired to replace outdated existing microprocessors, hereinafter referred to as legacy microprocessors, with newer microprocessors, hereinafter referred to as host microprocessors. Unfortunately, depending on the particular upgrade, most times the instruction set of the host microprocessor is incompatible with the instruction set of the legacy microprocessor.
One way to solve this problem is to rewrite the existing application program taking into account the instruction set of the host microprocessor. Such a technique is relatively cumbersome and quite expensive. In order to work around instruction set incompatibilities, software systems are known for emulating instructions of legacy microprocessors. Such systems are often referred to as emulation systems. Such emulation systems are known to emulate the instruction set of the legacy microprocessor in order to enable the application programs written in terms of the instruction set for the legacy microprocessor to be executed by a newer, faster host microprocessor.
In many known emulation systems, legacy instructions are fetched by the host microprocessor, which, in turn, uses a look-up table to interpret the legacy instruction. With such emulation systems, since each legacy instruction must be interpreted, systems which incorporate cache memory are known to suffer from relatively high probability of cache misses, which decreases the overall throughput of the system.
In order to improve the throughput or speed of such emulation systems, commonly owned U.S. Pat. No. 6,041,402 discloses a direct vectored legacy instruction set emulation system. Rather than fetching legacy instructions and interpreting the instructions in software, the direct vectored legacy instruction set emulation system fetches direct vectors to software routines which emulate the legacy instructions. By fetching the direct vectors, the need for look-up tables for interpreting the legacy instructions is eliminated. Since look-up table accesses are eliminated with such a system, the probability of cache misses is greatly reduced, which, in turn, increases the throughput of the system. Unfortunately, the direct vectored legacy instruction set emulation requires too much performance overhead for relatively modern microprocessors, such as 32-bit RISC microprocessors. Thus, there is a need for an emulation system and method for emulating instructions of legacy microprocessors which provides improved real-time performance relative to known emulation systems.